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19-2776; Rev 2; 12/03
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
General Description
The MAX5886 is an advanced, 12-bit, 500Msps digitalto-analog converter (DAC) designed to meet the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from a single 3.3V supply, this DAC offers exceptional dynamic performance such as 76dBc spurious-free dynamic range (SFDR) at fOUT = 30MHz. The DAC supports update rates of 500Msps and a power dissipation of only 230mW. The MAX5886 utilizes a current-steering architecture, which supports a full-scale output current range of 2mA to 20mA, and allows a differential output voltage swing between 0.1VP-P and 1VP-P. The MAX5886 features an integrated 1.2V bandgap reference and control amplifier to ensure high accuracy and low noise performance. Additionally, a separate reference input pin enables the user to apply an external reference source for optimum flexibility and to improve gain accuracy. The digital and clock inputs of the MAX5886 are designed for differential low-voltage differential signal (LVDS)-compatible voltage levels. The MAX5886 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended industrial temperature range (-40C to +85C). Refer to the MAX5887 and MAX5888 data sheets for pin-compatible 14- and 16-bit versions of the MAX5886. o 500Msps Output Update Rate o Single 3.3V Supply Operation o Excellent SFDR and IMD Performance SFDR = 76dBc at fOUT = 30MHz (to Nyquist) IMD = -85dBc at fOUT = 10MHz ACLR = 70dB at fOUT = 61MHz o 2mA to 20mA Full-Scale Output Current o Differential, LVDS-Compatible Digital and Clock Inputs o On-Chip 1.2V Bandgap Reference o Low 130mW Power Dissipation o 68-Pin QFN-EP Package
Features
MAX5886
Ordering Information
PART MAX5886EGK TEMP RANGE -40C to +85C PIN-PACKAGE 68 QFN-EP*
*EP = Exposed paddle.
Pin Configuration
DGND DGND DVDD B0N B1N B2N B3N B4N B5N B0P B1P B3P B4P B2P B5P B6P
51 B7N 50 B7P 49 B8N 48 B8P 47 B9N 46 B9P 45 B10N 44 B10P 43 B11N 42 B11P 41 DGND 40 DVDD 39 SEL0 38 N.C. 37 N.C. 36 N.C. 35 N.C.
TOP VIEW
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52
Applications
N.C.
1 2 3 4 5 6 7 8 9
EP
Base Stations: Single/Multicarrier UMTS, CDMA, GSM Communications: LMDS, MMDS, Point-to-Point Microwave Digital Signal Synthesis Automated Test Equipment (ATE) Instrumentation
N.C. N.C. N.C. N.C. N.C. N.C. N.C. DGND
MAX5886
DVDD 10 VCLK 11 CLKGND 12 CLKP 13 CLKN 14 CLKGND 15 VCLK 16 PD 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
AGND
REFIO
DACREF
IOUTN
FSADJ
IOUTP
N.C.
AGND
AGND
AGND
AGND
B6N
AVDD
AVDD
AVDD
AVDD
QFN
________________________________________________________________ Maxim Integrated Products
AVDD
N.C.
1
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886
ABSOLUTE MAXIMUM RATINGS
AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9V AVDD, DVDD, VCLK to DGND ...............................-0.3V to +3.9V AVDD, DVDD, VCLK to CLKGND ...........................-0.3V to +3.9V AGND, CLKGND to DGND....................................-0.3V to +0.3V DACREF, REFIO, FSADJ to AGND.............-0.3V to AVDD + 0.3V IOUTP, IOUTN to AGND................................-1V to AVDD + 0.3V CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V B0P/B0N-B11P/B11N, SEL0, PD to DGND ...........................................-0.3V to DVDD + 0.3V Continuous Power Dissipation (TA = +70C) 68-Pin QFN-EP (derate 41.7mW/C above +70C) ......3333mW Thermal Resistance (JA) ..............................................+24C/W Operating Temperature Range ..........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range ............................-60C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO = 1.25V, differential transformer-coupled analog output, 50 double terminated (Figure 7), IOUT = 20mA, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Drift Full-Scale Gain Error Gain Drift Full-Scale Output Current Min Output Voltage Max Output Voltage Output Resistance Output Capacitance DYNAMIC PERFORMANCE Output Update Rate Noise Spectral Density Spurious-Free Dynamic Range to Nyquist fCLK fCLK = 100MHz fCLK = 200MHz SFDR fCLK = 100MHz fOUT = 16MHz, -12dB FS fOUT = 80MHz, -12dB FS fOUT = 1MHz, 0dB FS fOUT = 1MHz, -6dB FS fOUT = 1MHz, -12dB FS 1 -151 -154 88 86 80 dBc 500 Msps dB FS/ Hz ROUT COUT IOUT GEFS External reference, TA +25C Internal reference External reference (Note 1) Single ended Single ended 2 -0.5 1.1 1 5 -3.5 100 50 20 INL DNL OS Measured differentially Measured differentially -0.025 12 0.2 0.15 0.01 50 +1.5 +0.025 Bits LSB LSB %FS ppm/C %FS ppm/C mA V V M pF SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO = 1.25V, differential transformer-coupled analog output, 50 double terminated (Figure 7), IOUT = 20mA, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS fCLK = 100MHz fOUT = 10MHz, -12dB FS fOUT = 30MHz, -12dB FS fOUT = 10MHz, -12dB FS fCLK = 200MHz SFDR fOUT = 16MHz, -12dB FS, TA +25C fOUT = 50MHz, -12dB FS fOUT = 80MHz, -12dB FS fOUT = 10MHz, -12dB FS fCLK = 500MHz fOUT = 30MHz, -12dB FS fOUT = 50MHz, -12dB FS fOUT = 80MHz, -12dB FS fCLK = 200MHz 2-Tone IMD TTIMD fCLK = 200MHz 4-Tone IMD, 1MHz Frequency Spacing, GSM Model Adjacent Channel Leakage Power Ratio, 4.1MHz Bandwidth, WCDMA Model Output Bandwidth REFERENCE Internal Reference Voltage Range Reference Voltage Drift Reference Input Compliance Range Reference Input Resistance ANALOG OUTPUT TIMING Output Fall Time Output Rise Time Output Voltage Settling Time Output Propagation Delay Glitch Energy Output Noise TIMING CHARACTERISTICS Data to Clock Setup Time Data to Clock Hold Time tSETUP tHOLD Referenced to rising edge of clock (Note 4) Referenced to rising edge of clock (Note 4) -0.8 1.8 ns ns NOUT IOUT = 2mA IOUT = 20mA tFALL tRISE tSETTLE tPD 90% to 10% (Note 3) 10% to 90% (Note 3) Output settles to 0.025% FS (Note 3) (Note 3) 375 375 11 1.8 1 30 30 ps ps ns ns pV-s pA/Hz VREFIO TCOREF VREFIOCR RREFIO 0.1 10 1.12 1.22 50 1.25 1.32 V ppm/C V k FTIMD fCLK = 300MHz fCLK = 184.32MHz (Note 2) fOUT1 = 9MHz, -6dB FS, fOUT2 = 10MHz, -6dB FS fOUT1 = 79MHz, -6dB FS, fOUT2 = 80MHz, -6dB FS fOUT = 32MHz, -12dB FS 69 MIN TYP 81 76 71 76 72 64 66 63 65 58 -85 dBc -61 -78 dBc dBc MAX UNITS
MAX5886
Spurious-Free Dynamic Range to Nyquist
ACLR BW-1dB
fOUT = 61.44MHz
70 450
dB MHz
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3
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO = 1.25V, differential transformer-coupled analog output, 50 double terminated (Figure 7), IOUT = 20mA, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Data Latency Minimum Clock Pulse Width High tCH CLKP, CLKN Minimum Clock Pulse Width Low tCL CLKP, CLKN LVDS LOGIC INPUTS (B0N-B11N, B0P-B11P) Differential Input Logic High Differential Input Logic Low Common-Mode Voltage Range Differential Input Resistance Input Capacitance CMOS LOGIC INPUTS (PD, SEL0) Input Logic High Input Logic Low Input Leakage Current Input Capacitance CLOCK INPUTS (CLKP, CLKN) Differential Input Voltage Swing Differential Input Slew Rate Common-Mode Voltage Range Input Resistance Input Capacitance POWER SUPPLIES Analog Supply Voltage Range Digital Supply Voltage Range Clock Supply Voltage Range Analog Supply Current Digital Supply Current Clock Supply Current AVDD DVDD VCLK IAVDD IDVDD IVCLK fCLK = 100Msps, fOUT = 1MHz Power-down fCLK = 100Msps, fOUT = 1MHz Power-down fCLK = 100Msps, fOUT = 1MHz Power-down 3.135 3.135 3.135 3.3 3.3 3.3 27 0.3 6.4 10 5.6 10 3.465 3.465 3.465 V V V mA mA A mA A VCLK SRCLK VCOM RCLK CCLK Sine wave Square wave (Note 5) 1.5 0.5 >100 1.5 20% 5 5 VP-P V/s V k pF VIH VIL IIN CIN -15 5 0.7 x DVDD 0.3 x DVDD +15 V V A pF VIH VIL VCOM RIN CIN 1.125 85 100 5 100 -100 1.375 125 SYMBOL CONDITIONS MIN TYP 3.5 0.9 0.9 MAX UNITS Clock cycles ns ns mV mV V pF
4
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO = 1.25V, differential transformer-coupled analog output, 50 double terminated (Figure 7), IOUT = 20mA, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Power Dissipation Power-Supply Rejection Ratio SYMBOL PDISS PSRR Power-down AVDD = VCLK = DVDD = 3.3V 5% (Note 6) -1 CONDITIONS fCLK = 100Msps, fOUT = 1MHz MIN TYP 130 1 +1 MAX . UNITS mW % FS/V
MAX5886
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Nominal full-scale current IOUT = 32 IREF. This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5886. Parameter measured single ended into a 50 termination resistor. Parameter guaranteed by design. A differential clock input slew rate of >100V/s is required to achieve the specified dynamic performance. Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage.
Typical Operating Characteristics
(AVDD = DVDD = VCLK = 3.3V, external reference, VREFIO = 1.25V, RL = 50, IOUT = 20mA, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 100MHz)
MAX5886 toc01
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 200MHz)
MAX5886 toc02
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 500MHz)
90 80 70 SFDR (dBc) 60 50 40 30 20 10 0 0dB FS -6dB FS -12dB FS
MAX5886 toc03
100 90 80 70 SFDR (dBc) 60 50 40 30 20 10 0 0 10 20 30 40 -6dB FS 0dB FS -12dB FS
100 90 80 70 SFDR (dBc) 60 50 40 30 20 10 0 -6dB FS 0dB FS -12dB FS
100
50
10
20
30
40
50
60
70
80
90 100
5
55
105
155
205
255
fOUT (MHz)
fOUT (MHz)
fOUT (MHz)
2-TONE INTERMODULATION DISTORTION (fCLK = 100MHz)
MAX5886 toc04
2-TONE IMD vs. OUTPUT FREQUENCY (1MHz CARRIER SPACING, fCLK = 200MHz)
MAX5886 toc05
2-TONE INTERMODULATION DISTORTION (fCLK = 500MHz)
-10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90 2 x fT1 - fT2 2 x fT2 - fT1 fT1 fT2 AOUT = -6dB FS BW = 12MHz fT1 = 78.7964MHz fT2 = 79.7729MHz
MAX5886 toc06
0 -10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90 -100 3 5 7 9 fOUT (MHz) 11 13 2 x fT1 - fT2 2 x fT2 - fT1 fT1 fT2 AOUT = -6dB FS BW = 12MHz fT1 = 8.9478MHz fT2 = 9.8999MHz
-100
0
-90 TWO-TONE IMD (dBc)
-12dB FS
-80
-70 -6dB FS
-60
-50 15 10 20 30 40 50 60 70 80 fOUT (MHz)
-100 74 76 78 80 fOUT (MHz) 82 84 86
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886
Typical Operating Characteristics (continued)
(AVDD = DVDD = VCLK = 3.3V, external reference, VREFIO = 1.25V, RL = 50, IOUT = 20mA, TA = +25C, unless otherwise noted.)
SFDR vs. OUTPUT FREQUENCY (fCLK = 300MHz, AOUT = -6dB FS)
MAX5886 toc07
SFDR vs. TEMPERATURE (fCLK = 300MHz, AOUT = -6dB FS, IOUT = 20mA)
fOUT = 10MHz 77 fOUT = 40MHz 0.1
MAX5886 toc08
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5886 toc09
100 80 IOUT = 20mA
85
0.3 0.2
SFDR (dBc)
SFDR (dBc)
69 fOUT = 120MHz
INL (LSB)
60
0 -0.1
40
IOUT = 5mA IOUT = 10mA
61
20
53
fOUT = 80MHz
-0.2 -0.3
0 0 30 60 90 120 150 fOUT (MHz)
45 -40 -15 10 35 60 85 TEMPERATURE (C)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARTIY vs. DIGITAL INPUT CODE
MAX5886 toc10
8-TONE MULTITONE POWER RATIO PLOT (fCLK = 300MHz, fCENTER = 31.6040MHz)
-10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90 fT1 fT2 fT3 fT4 fT5 fT6 fT7 fT8 AOUT = -18dB FS BW = 12MHz
MAX5886 toc11
0.3 0.2 0.1 DNL (LSB) 0 -0.1 -0.2 -0.3
0
-100 0 500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL INPUT CODE 26 28 30 32 fOUT (MHz) 34 36 38
fT1 = 27.8687MHz fT2 = 28.8208MHz fT3 = 29.6997MHz fT4 = 30.7251MHz
fT5 = 32.4829MHz fT6 = 34.0209MHz fT7 = 34.8999MHz fT8 = 35.9985MHz
POWER DISSIPATION vs. CLOCK FREQUENCY (fOUT = 10MHz, AOUT = 0dB FS, IOUT = 20mA)
MAX5886 toc12
POWER DISSIPATION vs. SUPPLY VOLTAGE (fCLK = 100MHz, fOUT = 10MHz, IFS = 20mA)
MAX5886 toc13
280 240
150 145 POWER DISSIPATION (mW) 140 135 INTERNAL REFERENCE 130 125 120 EXTERNAL REFERENCE
POWER DISSIPATION (mW)
200
160
120
80 100 200 300 fCLK (MHz) 400 500
3.135 3.190
3.245 3.300
3.355 3.410
3.465
SUPPLY VOLTAGE (V)
6
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
Pin Description
PIN 1-8, 23, 34, 35-38 9, 41, 60, 62 10, 40, 61 11, 16 12, 15 13 14 17 18, 24, 29, 30, 32 19, 25, 28, 31, 33, EP 20 21 22 26 27 NAME N.C. DGND DVDD VCLK CLKGND CLKP CLKN PD AVDD AGND REFIO FSADJ DACREF IOUTN IOUTP FUNCTION Not connected. Do not connect to these pins. Do not tie these pins together. Digital Ground Digital Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a 0.1F capacitor to the nearest DGND. Clock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a 0.1F capacitor to the nearest CLKGND. Clock Ground Converter Clock Input. Positive input terminal for LVDS-compatible differential converter clock. Complementary Converter Clock Input. Negative input terminal for the LVDS-compatible differential converter clock. Power-Down Input. PD pulled high enables the DAC's power-down mode. PD pulled low allows for normal operation of the DAC. This pin features an internal pulldown resistor. Analog Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a 0.1F capacitor to the nearest AGND. Analog Ground. Exposed paddle (EP) must be connected to AGND. Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1F capacitor to AGND. Can be driven with an external reference source. Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For 20mA full-scale output current, connect a 2k resistor between FSADJ and DACREF. Return Path for the Current Set Resistor. For 20mA full-scale output current, connect a 2k resistor between FSADJ and DACREF. Complementary DAC Output. Negative terminal for differential current output. The full-scale output current range can be set from 2mA to 20mA. DAC Output. Positive terminal for differential current output. The full-scale output current range can be set from 2mA to 20mA. Mode Select Input SEL0. Set high to activate the segment shuffling function. Since this pin features an internal pulldown resistor, it can be left open or pulled low to disable the segment-shuffling function. See Segment Shuffling in the Detailed Description section for more information. Data Bit 11 (MSB) Complementary Data Bit 11 (MSB) Data Bit 10 Complementary Data Bit 10 Data Bit 9
MAX5886
39 42 43 44 45 46
SEL0 B11P B11N B10P B10N B9P
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7
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886
Pin Description (continued)
PIN 47 48 49 50 51 52 53 54 55 56 57 58 59 63 64 65 66 67 68 NAME B9N B8P B8N B7P B7N B6P B6N B5P B5N B4P B4N B3P B3N B2P B2N B1P B1N B0P B0N Complementary Data Bit 9 Data Bit 8 Complementary Data Bit 8 Data Bit 7 Complementary Data Bit 7 Data Bit 6 Complementary Data Bit 6 Data Bit 5 Complementary Data Bit 5 Data Bit 4 Complementary Data Bit 4 Data Bit 3 Complementary Data Bit 3 Data Bit 2 Complementary Data Bit 2 Data Bit 1 Complementary Data Bit 1 Data Bit 0 Complementary Data Bit 0 FUNCTION
Detailed Description
Architecture
The MAX5886 is a high-performance, 12-bit, currentsteering DAC (Figure 1) capable of operating with clock speeds up to 500MHz. The converter consists of separate input and DAC registers, followed by a currentsteering circuit. This circuit is capable of generating differential full-scale currents in the range of 2mA to 20mA. An internal current-switching network in combination with external 50 termination resistors convert the differential output currents into a differential output voltage with a peak-to-peak output voltage range of 0.1V to 1V. An integrated 1.2V bandgap reference, control amplifier, and user-selectable external resistor determine the data converter's full-scale output range.
limited output drive capability REFIO must be buffered with an external amplifier, if heavier loading is required. The MAX5886's reference circuit (Figure 2) employs a control amplifier, designed to regulate the full-scale current IOUT for the differential current outputs of the DAC. Configured as a voltage-to-current amplifier, the output current can be calculated as follows: IOUT = 32 IREFIO - 1 LSB IOUT = 32 IREFIO - (IOUT / 212) where IREFIO is the reference output current (IREFIO = VREFIO/RSET) and IOUT is the full-scale output current of the DAC. Located between FSADJ and DACREF, RSET is the reference resistor, which determines the amplifier's output current for the DAC. See Table 1 for a matrix of different IOUT and RSET selections.
Reference Architecture and Operation
The MAX5886 supports operation with the on-chip 1.2V bandgap reference or an external reference voltage source. REFIO serves as the input for an external, lowimpedance reference source, and as the output if the DAC is operating with the internal reference. For stable operation with the internal reference, REFIO should be decoupled to AGND with a 0.1F capacitor. Due to its
8
Analog Outputs (IOUTP, IOUTN)
The MAX5886 outputs two complementary currents (IOUTP, IOUTN) that can be operated in a single-ended or differential configuration. A load resistor can convert these two output currents into complementary single-
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886
DVDD DGND SEL0 PD
1.2V REFERENCE
FUNCTION SELECTION BLOCK
AGND AVDD
MAX5886
REFIO CURRENT-STEERING DAC IOUTP IOUTN
FSADJ
CLKN CLKP
SEGMENT SHUFFLING/LATCH
DECODER
LVDS RECEIVER/INPUT LATCH
12 DIFFERENTIAL DIGITAL INPUTS B0 THROUGH B11
Figure 1. Simplified MAX5886 Block Diagram
Table 1. IOUT and RSET Selection Matrix Based on a Typical 1.200V Reference Voltage
FULL-SCALE CURRENT IOUT (mA) 2 5 10 15 20 REFERENCE CURRENT IREF (A) 62.5 156.25 312.5 468.75 625 RSET (k) CALCULATED 19.2 7.68 3.84 2.56 1.92 1% EIA STD 19.1 7.5 3.83 2.55 1.91 OUTPUT VOLTAGE VIOUTP/N* (mVP-P) 100 250 500 750 1000
*Terminated into a 50 load.
ended output voltages. The differential voltage existing between IOUTP and IOUTN can also be converted to a single-ended voltage using a transformer or a differential amplifier configuration. If no transformer is used, the output should have a 50 termination to the analog ground and a 50 resistor between the outputs.
Although not recommended because of additional noise pickup from the ground plane, for single-ended operation IOUTP should be selected as the output, with IOUTN connected to AGND. Note that a single-ended output configuration has a higher 2nd-order harmonic distortion at high output frequencies than a differential output configuration.
9
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886
AVDD
1.2V REFERENCE
AVDD CURRENT SOURCES
10k REFIO 0.1F
CURRENT SWITCHES
FSADJ IREF RSET DACREF IREF = VREFIO/RSET CURRENT-STEERING DAC
IOUTP
IOUT IOUT IOUTN IOUTP
IOUTN
Figure 2. Reference Architecture, Internal Reference Configuration
Figure 3. Simplified Analog Output Structure
Figure 3 displays a simplified diagram of the MAX5886's internal output structure.
WIDEBAND RF TRANSFORMER PERFORMS SINGLE-ENDED TO DIFFERENTIAL CONVERSION.
0.1F CLKP 25
Clock Inputs (CLKP, CLKN)
The MAX5886 features a flexible differential clock input (CLKP, CLKN) operating from separate supplies (VCLK, CLKGND) to achieve the lowest possible jitter performance. The two clock inputs can be driven from a single-ended or a differential clock source. For single-ended operation, CLKP should be driven by a logic source, while CLKN should be bypassed to AGND with a 0.1F capacitor. The CLKP and CLKN pins are internally biased to 1.5V. This allows the user to AC-couple clock sources directly to the device without external resistors to define the DC level. The input resistance of CLKP and CLKN is >5k. See Figure 4 for a convenient and quick way to apply a differential signal created from a single-ended source (e.g., HP 8662A signal generator) and a wideband transformer. These inputs can also be driven from an LVDS-compatible clock source; however, it is recommended to use sinewave or AC-coupled ECL drive for best performance.
1:1 SINGLE-ENDED CLOCK SOURCE (e.g., HP 8662A)
TO DAC 25
0.1F
CLKN
CLKGND
Figure 4. Differential Clock Signal Generation
cycle latency between CLKP/CLKN transitioning high/low and IOUTP/IOUTN.
LVDS-Compatible Digital Inputs (B0P-B11P, B0N-B11N)
The MAX5886 features LVDS receivers on the bus input interface. These LVDS inputs (B0P/N through B11P/N) allow for a low-differential voltage swing with low constant power consumption across a large range of frequencies. Their differential characteristic supports the transmission of high-speed data patterns without the negative effects of electromagnetic interference (EMI). All MAX5886 LVDS inputs feature on-chip termination with differential 100 resistors. See Figure 6 for a simplified block diagram of the LVDS inputs.
Data Timing Relationship
Figure 5 shows the timing relationship between differential, digital LVDS data, clock, and output signals. The MAX5886 features a 1.8ns hold, a -0.8ns setup, and a 1.8ns propagation delay time. There is a 3.5 clock10
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886
DIGITAL DATA IS LATCHED ON THE RISING EDGE OF CLKP OUTPUT DATA IS UPDATED ON THE FALLING EDGE OF CLKP
B0 TO B15
N-1
N
N+1
N+2
tSETUP
tHOLD
tCH
tCL
CLKP
CLKN tPD
IOUT
N-5
N-4
N-3
N-2
N-1
Figure 5. Detailed Timing Relationship
A common-mode level of 1.25V and an 800mV differential input swing can be applied to these inputs. Segment Shuffling (SEL0) Segment shuffling can improve the SFDR of the MAX5886. The improvement is most pronounced at higher output frequencies and amplitudes. Note that an improvement in SFDR can only be achieved at the cost of a slight increase in the DAC's noise floor. Pin SEL0 controls the segment-shuffling function. If SEL0 is pulled low, the segment-shuffling function of the DAC is disabled. SEL0 can also be left open, because an internal pulldown resistor helps to deactivate the segment-shuffling feature. To activate the MAX5886 segment-shuffling function, SEL0 must be pulled high. Power-Down Operation (PD) The MAX5886 also features an active-high power-down mode, which allows the user to cut the DAC's current consumption. A single pin (PD) is used to control the power-down mode (PD = 1) or reactivate the DAC (PD = 0) after power-down. Enabling the power-down mode of the MAX5886 allows the overall power consumption to be reduced to less than 1mW. The MAX5886 requires 10ms to wake up from power-down and enter a fully operational state.
B0P-B11P D 100 D B0N-B11N CLOCK Q Q TO DECODE LOGIC
Figure 6. Simplified LVDS-Compatible Input Structure
Applications Information
Differential Coupling Using a Wideband RF Transformer
The differential voltage existing between IOUTP and IOUTN can also be converted to a single-ended voltage using a transformer (Figure 7) or a differential amplifier configuration. Using a differential transformercoupled output, in which the output power is limited to 0dBm, can optimize the dynamic performance. However, make sure to pay close attention to the transformer core saturation characteristics when selecting a transformer for the MAX5886. Transformer core saturation can introduce strong 2nd-harmonic distortion, especially at low output frequencies and high signal amplitudes. It is also recommended to center tap the transformer to ground. If no transformer is used, each DAC output should be terminated to ground with a 50 resistor. Additionally, a 100 resistor should be placed between the outputs (Figure 8).
11
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886
AVDD DVDD VCLK 50 T2, 1:1 B0-B11 IOUTP VOUT, SINGLE ENDED
MAX5886
12 IOUTN
100
T1, 1:1 AGND DGND CLKGND 50 WIDEBAND RF TRANSFORMER T2 PERFORMS THE DIFFERENTIAL TO SINGLE-ENDED CONVERSION.
Figure 7. Differential to Single-Ended Conversion Using a Wideband RF Transformer
AVDD
DVDD
VCLK 50 OUTP 100 IOUTN OUTN 50
Adjacent Channel Leakage Power Ratio (ACLR) Testing for CDMA- and W-CDMA-Based Base Station Transceiver Systems (BTS)
The transmitter sections of BTS applications serving CDMA and W-CDMA architectures must generate carriers with minimal coupling of carrier energy into the adjacent channels. Similar to the GSM/EDGE model (see the Multitone Testing for GSM/EDGE Applications section), a transmit mask (Tx mask) exists for this application. The spread-spectrum modulation function applied to the carrier frequency generates a spectral response, which is uniform over a given bandwidth (up to 4MHz) for a W-CDMA-modulated carrier. A dominant specification is ACLR, a parameter which reflects the ratio of the power in the desired carrier band to the power in an adjacent carrier band. The specification covers the first two adjacent bands, and is measured on both sides of the desired carrier. According to the transmit mask for CDMA and W-CDMA architectures, the power ratio of the integrated carrier channel energy to the integrated adjacent channel energy must be >45dB for the first adjacent carrier slot (ACLR 1) and >50dB for the second adjacent carrier slot (ACLR 2). This specification applies to the output of the entire transmitter signal chain. The requirement for only the DAC block of the transmitter must be tighter, with a typical margin of >15dB, requiring the DAC's ACLR 1 to be better than 60dB. Adjacent channel leakage is caused by a single spread-spectrum carrier, which generates intermodulation (IM) products
B0-B11
IOUTP
MAX5886
12
AGND
DGND
CLKGND
Figure 8. MAX5886 Differential Output Configuration
If a single-ended unipolar output is desirable, IOUTP should be selected as the output, with IOUTN grounded. However, driving the MAX5886 single ended is not recommended since additional noise is added (from the ground plane) in such configurations. The distortion performance of the DAC depends on the load impedance. The MAX5886 is optimized for a 50 double termination. It can be used with a transformer output as shown in Figure 7 or just one 50 resistor from each output to ground and one 50 resistor between the outputs. This produces a full-scale output power of up to 0dBm depending on the output current setting. Higher termination impedance can be used at the cost of degraded distortion performance and increased output noise voltage.
12
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
between the frequency components located within the carrier band. The energy at one end of the carrier band generates IM products with the energy from the opposite end of the carrier band. For single-carrier W-CDMA modulation, these IMD products are spread 3.84MHz over the adjacent sideband. Four contiguous W-CDMA carriers spread their IM products over a bandwidth of 20MHz on either side of the 20MHz total carrier bandwidth. In this four-carrier scenario, only the energy in the first adjacent 3.84MHz side band is considered for ACLR 1. To measure ACLR, drive the converter with a W-CDMA pattern. Make sure that the signal is backed off by the peak-to-average ratio, such that the DAC is not clipping the signal. ACLR can then be measured with the ACLR measurement function built into your spectrum analyzer. Figure 9 shows the ACLR performance for a single W-CDMA carrier (fCLK = 184.32MHz, fOUT = 61.44MHz) applied to the MAX5886 (including measurement system limitations*). Figure 10 illustrates the ACLR test results for the MAX5886 with a four-carrier W-CDMA signal at an output frequency of 63.98MHz and sampling frequency of 184.32MHz. Considerable care must be taken to ensure accurate measurement of this parameter. communication DAC manufacturers with the difficult task of providing devices with higher resolution, while simultaneously reducing noise and spurious emissions over a desired bandwidth. To specify noise and spurious emissions from base stations, a GSM/EDGE Tx mask is used to identify the DAC requirements for these parameters. This mask shows that the allowable levels for noise and spurious emissions are dependent on the offset frequency from the transmitted carrier frequency. The GSM/EDGE mask and its specifications are based on a single active carrier with any other carriers in the transmitter being disabled. Specifications displayed in Figure 11 support per-carrier output power levels of 20W or greater. Lower output power levels yield less-stringent emission requirements. For GSM/EDGE applications, the DAC demands spurious emission levels of less than -80dBc for offset frequencies 6MHz. Spurious products from the DAC can combine with both random noise and spurious products from other circuit elements. The spurious products from the DAC should therefore be backed off by 6dB or more to allow for these other sources and still avoid signal clipping. The number of carriers and their signal levels with respect to the full scale of the DAC are important as well. Unlike a full-scale sine wave, the inherent nature of a multitone signal contains higher peak-to-RMS ratios, raising the prospect for potential clipping, if the signal level is not backed off appropriately. If a transmitter operates with four/eight in-band carriers, each
MAX5886
Multitone Testing for GSM/EDGE Applications
The transmitter sections of multicarrier base station transceiver systems for GSM/EDGE usually present
ANALOG OUTPUT POWER (dBm)
-60 -70 -80 -90 -100 -110 -120 -130 -140 -145 3.5MHz/div
ANALOG OUTPUT POWER (dBm)
-25 -30 -40 -50
fCENTER = 61.44MHz fCLK = 184.32Mbps ACLR = 70dB
-25 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -145 fCENTER = 63.98MHz fCLK = 184.32Mbps ACLR = 63dB 3.5MHz/div
Figure 9. ACLR for W-CDMA Modulation, Single Carrier
Figure 10. ACLR for W-CDMA Modulation, Four Carriers
*Note that due to their own IM effects and noise limitations, spectrum analyzers introduce ACLR errors, which can falsify the measurement. For a single-carrier ACLR measurement greater than 70dB, these measurement limitations are significant, becoming even more restricting for multicarrier measurement. Before attempting an ACLR measurement, it is recommended consulting application notes provided by major spectrum analyzer manufacturers that provide useful tips on how to use their instruments for such tests. ______________________________________________________________________________________ 13
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886
individual carrier must be operated at less than -12dB FS/-18dB FS to avoid waveform clipping. The noise density requirements (Table 2) for a GSM/EDGE-based system can again be derived from the system's Tx mask. With a worst-case noise level of -80dBc at frequency offsets of 6MHz and a measurement bandwidth of 100kHz, the minimum noise density per hertz is calculated as follows: SNRMIN = -80dBc - 10 log10(100 103Hz) SNRMIN = -130dBc/Hz Since random DAC noise adds to both the spurious tones and to random noise from other circuit elements, it is recommended reducing the specification limits by about 10dB to allow for these additional noise contributions while maintaining compliance with the Tx mask values. Other key factors in selecting the appropriate DAC for the Tx path of a multicarrier GSM/EDGE system is the converter's ability to offer superior IMD and MTPR performance. Multiple carriers in a designated band generate unwanted intermodulation distortion between the individual carrier frequencies. A multitone test vector usually consists of several equally spaced carriers, usually four, with identical amplitudes. Each of these carriers is representative of a channel within the defined bandwidth of interest. To verify MTPR, one or more tones are removed such that the intermodulation distortion performance of the DAC can be evaluated. Nonlinearities associated with the DAC create spurious tones, some of which may fall back into the area of the removed tone, limiting a channel's carrier-to-noise ratio. Other spurious components falling outside the band of interest can also be important, depending on the system's spectral mask and filtering requirements. Going back to
Table 2. GSM/EDGE Noise Requirements for Multicarrier Systems
NUMBER OF CARRIERS 2 4 CARRIER POWER LEVEL (dB FS) -6 -12 DAC NOISE DENSITY REQUIREMENT (dB FS/Hz) -146 -152
the GSM/EDGE Tx mask, the IMD specification for adjacent carriers varies somewhat among the different GSM standards. For the PCS1800 and GSM850 standards, the DAC must meet an average IMD of -70dBc. Table 3 summarizes the dynamic performance requirements for the entire Tx signal chain in a four-carrier GSM/EDGE-based system and compares the previously established converter requirements with a new-generation high dynamic performance DAC. The four-tone MTPR plot in Figure 12 demonstrates the MAX5886's excellent dynamic performance. The center frequency (fCENTER = 32MHz) has been removed to allow detection and analysis of intermodulation or spurious components falling back into this empty spot from adjacent channels. The four carriers are observed over a 12MHz bandwidth and are equally spaced at 1MHz. Each individual output amplitude is backed off to -12dB FS. Under these conditions, the DAC yields an MTPR performance of -78dBc.
Grounding, Bypassing, and Power-Supply Considerations
Grounding and power-supply decoupling can strongly influence the performance of the MAX5886. Unwanted digital crosstalk may couple through the input, reference, power supply, and ground connections, affecting dynamic performance. Proper grounding and power-
Table 3. Summary of Important AC Performance Parameters for Multicarrier GSM/EDGE Systems
SPECIFICATION SFDR Noise Spectral Density IMD Carrier Amplitude SYSTEM TRANSMITTER OUTPUT LEVELS 80dBc -130dBc/Hz -70dBc N/S DAC REQUIREMENTS WITH MARGINS 86dBc -152dB FS/Hz -75dBc -12dB FS MAX5886 SPECIFICATIONS 90dBc* -154dB FS/Hz -85dBc -12dB FS
*Measured within a 15MHz window.
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886
4-TONE MULTITONE POWER RATIO PLOT (fCLK = 300MHz, fCENTER = 31.604MHz)
0
O INBAND TRANSMITTER EDGE OUTBAND
-10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90 -100 26
AOUT = -12dB FS BW = 12MHz fT1 fT2 fT3 fT4
AMPLITUDE (dBc)
-30
MEASUREMENT BANDWIDTH 30kHz 100kHz
-60 -70 -73 -75 -80 -90 0.2 0.4 0.6 1.2 1.8
IMD REQUIREMENT: < -70dBc WORST-CASE NOISE LEVEL
6.0
28
30
32 fOUT (MHz)
34
36
38
FREQUENCY OFFSET FROM CARRIER (MHz)
fT1 = 29.6997MHz fT2 = 30.7251MHz fT3 = 32.4829MHz fT4 = 34.0209MHz
Figure 11. GSM/EDGE Tx Mask Requirements
Figure 12. 4-Tone MTPR Test Results
supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. This reduces EMI and internal crosstalk that can significantly affect the dynamic performance of the MAX5886. Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. High-speed signals should run on lines directly above the ground plane. Since the MAX5886 has separate analog and digital ground buses (AGND, CLKGND, and DGND, respectively), the PC board should also have separate analog and digital ground sections with only one point connecting the two planes. Digital signals should be run above the digital ground plane and analog/clock signals above the analog/clock ground plane. Digital signals should be kept as far away from sensitive analog inputs, reference input sense lines, common-mode input, and clock inputs as practical. A symmetric design of clock input and analog output lines is recommended to minimize 2nd-order harmonic distortion components and optimize the DAC's dynamic performance. Digital signal paths should be kept short and run lengths matched to avoid propagation delay and data skew mismatches.
The MAX5886 supports three separate power-supply inputs for analog (AVDD), digital (DVDD), and clock (VCLK) circuitry. Each AVDD, DVDD, and VCLK input should at least be decoupled with a separate 0.1F capacitor as close to the pin as possible and their opposite ends with the shortest possible connection to the corresponding ground plane (Figure 13). Try to minimize the analog and digital load capacitances for optimized operation. All three power-supply voltages should also be decoupled at the point they enter the PC board with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors forming a pi network could also improve performance. The analog and digital power-supply inputs AV DD , VCLK, and DVDD of the MAX5886 allow a supply voltage range of 3.3V 5%. The MAX5886 is packaged in a 68-pin QFN-EP (package code: G6800-4), providing greater design flexibility, increased thermal efficiency**, and optimized AC performance of the DAC. The exposed pad (EP) enables the user to implement grounding techniques, which are necessary to ensure highest performance operation. The EP must be soldered down to AGND.
**Thermal efficiency is not the key factor, since the MAX5886 features low-power operation. The exposed pad is the key element to ensure a solid ground connection between the DAC and the PC board's analog ground layer.
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15
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR) flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (6mm 6mm), ensures the proper attachment and grounding of the DAC. Designing vias*** into the land area and implementing large ground planes in the PC board design allow for highest performance operation of the DAC. An array of at least 4 4 vias (0.3mm diameter per via hole and 1.2mm pitch between via holes) is recommended for this 68-pin QFN-EP package.
MAX5886
Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. Offset Error The offset error is the difference between the ideal and the actual offset current. For a DAC, the offset point is the average value at the output for the two midscale digital input codes with respect to the full scale of the DAC. This error affects all codes by the same amount. Gain Error A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter's specified accuracy.
Static Performance Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step.
***Vias connect the land pattern to internal or external copper planes. It is important to connect as many vias as possible to the analog ground plane to minimize inductance.
BYPASSING--DAC LEVEL AVCC AVDD VCLK
BYPASSING--BOARD LEVEL
FERRITE BEAD ANALOG POWER-SUPPLY SOURCE
0.1F
0.1F
1F
10F
47F
AGND
CLKGND OUTP DVCC FERRITE BEAD
B0-B11
MAX5886
12 1F OUTN 10F 47F
DIGITAL POWER-SUPPLY SOURCE
0.1F
VCLK FERRITE BEAD
DGND 1F DVDD 10F 47F CLOCK POWER-SUPPLY SOURCE
Figure 13. Recommended Power-Supply Decoupling and Bypassing Circuitry 16 ______________________________________________________________________________________
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
Glitch Energy A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. The glitch energy is found by integrating the voltage of the glitch at the midscale transition over time. The glitch energy is usually specified in pV-s. rier frequency amplitude or in dB FS with respect to the DAC's full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist.
MAX5886
Two-/Four-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or dB FS) of either input tone to the worst 3rd-order (or higher) IMD products. Note that 2nd-order IMD products usually fall at frequencies that can be easily removed by digital filtering; therefore, they are not as critical as 3rd-order IMDs. The two-tone IMD performance of the MAX5886 was tested with the two individual input tone levels set to at least -6dB FS and the four-tone performance was tested according to the GSM model at an output frequency of 32MHz and amplitude of -12dB FS.
Dynamic Performance Parameter Definitions
Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog output (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum can be derived from the DAC's resolution (N bits): SNRdB = 6.02dB N + 1.76dB However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading; therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal components) to the RMS value of their next-largest distortion component. SFDR is usually measured in dBc and with respect to the car-
Adjacent Channel Leakage Power Ratio (ACLR)
Commonly used in combination with W-CDMA, ACLR reflects the leakage power ratio in dB between the measured power within a channel relative to its adjacent channel. ACLR provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited RF signal passes through a nonlinear device.
Chip Information
TRANSISTOR COUNT: 10,629 PROCESS: CMOS
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3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
68L QFN.EPS
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
MAX5886 Package Code: G6800-4
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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